VDP register reference
$80xx
: mode set register #1$81xx
: mode set register #2$82xx
: plane A table address$83xx
: window table address$84xx
: plane B table address$85xx
: sprite table address$87xx
: background color$8Axx
: hblank interrupt rate$8Bxx
: mode set register #3$8Cxx
: mode set register #4$8Dxx
: hscroll table address$8Fxx
: autoincrement$90xx
: tilemap size$91xx
: window X division$92xx
: window Y division$93xx
,$94xx
: DMA length$95xx
,$96xx
,$97xx
: DMA source
$80xx
: mode set register #1
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0
| 0
| LCB
| IE1
| 0
| 1
| M3
| 0
|
LCB
: 1 to blank the leftmost column (8px wide)IE1
: 1 to enable hblank interruptM3
: 1 to freeze HV counter
$81xx
: mode set register #2
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0
| DISP
| IE0
| M1
| M2
| 1
| 0
| 0
|
DISP
: 1 to enable renderingIE0
: 1 to enable vblank interruptM1
: 1 to allow DMA operationsM2
: vertical resolution in tiles0
: 28 tiles (V28 mode)1
: 30 tiles (V30 mode)
Note that V30 mode only works properly on PAL systems.
$82xx
: plane A table address
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0
| 0
| SA15
| SA14
| SA13
| 0
| 0
| 0
|
SA15-13
: plane A table base address (divided by$2000
)
$83xx
: window table address
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0
| 0
| WD15
| WD14
| WD13
| WD12
| WD11
| 0
|
WD15-11
: window table base address (divided by$800
). In H40 mode,WD11
must be 0.
$84xx
: plane B table address
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0
| 0
| 0
| 0
| 0
| SB15
| SB14
| SB13
|
SB15-13
: plane B table base address (divided by$2000
)
$85xx
: sprite table address
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0
| AT15
| AT14
| AT13
| AT12
| AT11
| AT10
| AT9
|
AT15-9
: sprite table base address (divided by$200
). In H40 mode,AT9
must be 0.
$87xx
: background color
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0
| 0
| CPT1
| CPT0
| COL3
| COL2
| COL1
| COL0
|
CPT1-0
: background color paletteCOL3-0
: background color index
$8Axx
: hblank interrupt rate
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
HIT7
| HIT6
| HIT5
| HIT4
| HIT3
| HIT2
| HIT1
| HIT0
|
HIT7-0
: how many lines to wait between hblank interrupts
$8Bxx
: mode set register #3
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0
| 0
| 0
| 0
| IE2
| VSCR
| HSCR
| LSCR
|
IE2
: 1 to enable external interruptVSCR
: vertical scroll mode0
: full scroll1
: scroll every two tiles
H/LSCR
: horizontal scroll mode00
: full scroll01
: scroll eight lines, then repeat10
: scroll every tile11
: scroll every line
$8Cxx
: mode set register #4
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
RS0
| 0
| 0
| 0
| S/TE
| LSM1
| LSM0
| RS1
|
RS0-1
: horizontal resolution in tiles00
: 32 tiles (H32 mode)11
: 40 tiles (H40 mode)
S/TE
: 1 to enable shadow/highlightLSM1-0
: interlaced mode00
: no interlacing01
: mode 1 (interlaced but no resolution increase)11
: mode 2 (interlaced with higher resolution)
$8Dxx
: hscroll table address
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0
| 0
| HS15
| HS14
| HS13
| HS12
| HS11
| HS10
|
HS15-10
: hscroll table base address (divided by$400
)
$8Fxx
: autoincrement
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
INC7
| INC6
| INC5
| INC4
| INC3
| INC2
| INC1
| INC0
|
INC7-0
: autoincrement amount (in bytes)
$90xx
: tilemap size
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
0
| 0
| VSZ1
| VSZ0
| 0
| 0
| HSZ1
| HSZ0
|
VSZ1-0
: vertical size (see below)HSZ1-0
: horizontal size (see below)
VSZ1-0
| HSZ1-0
| Size in tiles |
---|---|---|
00 | 00 | 32×32 |
00 | 01 | 64×32 |
00 | 11 | 128×32 |
01 | 00 | 32×64 |
01 | 01 | 64×64 |
11 | 00 | 32×128 |
Other tilemap sizes will not work as expected.
$91xx
: window X division
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
RIGT
| 0
| 0
| WHP5
| WHP4
| WHP3
| WHP2
| WHP1
|
RIGT
: where to display window0
: to the left of the split X coordinate1
: to the right of the split X coordinate
WHP5-1
: X coordinate of split (in 16px steps)
$92xx
: window Y division
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
DOWN
| 0
| 0
| WVP4
| WVP3
| WVP2
| WVP1
| WVP0
|
DOWN
: where to display window0
: above the split Y coordinate1
: below the split Y coordinate
WVP4-0
: Y coordinate of split (in 8px steps)
$93xx
,$94xx
: DMA length
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
LG7
| LG6
| LG5
| LG4
| LG3
| LG2
| LG1
| LG0
|
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
LG15
| LG14
| LG13
| LG12
| LG11
| LG10
| LG9
| LG8
|
LG15-0
: DMA length
$95xx
,$96xx
,$97xx
: DMA source
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
SA8
| SA7
| SA6
| SA5
| SA4
| SA3
| SA2
| SA1
|
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
SA16
| SA15
| SA14
| SA13
| SA12
| SA11
| SA10
| SA9
|
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
---|---|---|---|---|---|---|---|
DMD1
| DMD0
| SA22
| SA21
| SA20
| SA19
| SA18
| SA17
|
SA22-1
: DMA sourceDMD1-0
: DMA operation type0*
: DMA transfer (DMD0
becomesSA23
)10
: VRAM fill11
: VRAM copy